The present invention relates to a power saving device and, more particularly, to a power saving device applicable to a receiver of the type demodulating an FM (Frequency Modulation) signal.
It is a common practice with a portable telephone or similar miniature battery-powered portable electronic apparatus to use circuitry for reducing power consumption. A portable telephone, for example, is so constructed as to lower clock frequency while the telephone is in a stand-by state, as taught in Japanese Patent Laid-Open Publication No. 6-232797 by way of example.
However, even in the stand-by state, the above conventional telephone processes a control signal demodulated from a signal with a DSP (Digital Signal Processor). The DSP consumes substantial power even when the clock frequency is lowered, obstructing power saving in the stand-by state. In addition, a high frequency demodulation circuit used during conversation is used in the stand-by state also. Therefore, the demodulation circuit would aggravate power consumption in the stand-by state if provided with an quadrature detector and an AGC (Auto Gain Control) amplifier.
Technologies relating to the present invention are also disclosed in, e.g., Japanese Patent Laid-Open Publication Nos. 4-120920, 5-130012, 6-252798, 7-95144, 8-56248, 8-172389, and 8-172672.